Welcome to IEEE TCCA Email-Monthly, May 2005. 1. ISCA 2005: 32nd Annual International Symposium on Computer Architecture *Madison, Wisconsin (USA) June 4-8, 2005, *Submitted by: Craig Zilles *Call for Participation http://www.cs.wisc.edu/~isca2005/ 2. ISSPIT 2005: The 5th IEEE International Symposium on Signal Processing and Information Technology *December 18-21, 2005, Athens, Greece *Submission deadline: June 30, 2005 *Submitted by: Stefanos Kaxiras *CFP: http://www.isspit.org 3. IISWC 2005: The Annual IEEE Int'l Symposium on Workload Characterization *October 6-8, 2005, Austin, Texas *SUBMISSION DEADLINE: June 20, 2005 *Submitted by: Suleyman Sair, ssair@moss.csc.ncsu.edu *CALL FOR PAPERS: http://www.iiswc.org/ 4. HPCA-12 12th Int'l Symposium on High-Performance Computer Architecture *Austin, Texas, February 11-15, 2006 *SUBMISSION DEADLINE: July 11, 2005 *Submitted by: Ki Hwan Yum *Call for Papers: http://www.hpcaconf.org/hpca12 5. HiPEAC 2005: Int'l Conference on High Performance Embedded Architectures & Compilers *Barcelona, Spain, 17-18 November 2005 *SUBMISSION DEADLINE: June 10, 2005 *Submitted by: Sally McKee *Call for Papers: http://www.hipeac.net/hipeac2005 6. SBAC-PAD 2005 17th Int'l Symposium on Computer Architecture and High Performance Computing *Rio de Janeiro, October 24-27, 2005 *SUBMISSION DEADLINE: May 23, 2005 *Submitted by: Rajkumar Buyya *Call for Papers: http://www.sbc.org.br/sbac/2005 7. SNAPI'05: Int'l Workshop on Storage Network Architecture and Parallel I/Os *Saint Louis, Missouri, September 18, 2005 *SUBMISSION DEADLINE: July 10, 2005 *Call for Papers: http://rcf.unl.edu/~abacus/SNAPI_05/ ------- * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members, send an email to qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe ----------------------------------------------------------------------- Qing (Ken) Yang, Distinguished Engineering Professor e-mail: qyang@ele.uri.edu Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 University of Rhode Island Fax (401) 782-6422 Kingston RI. 02881 http://www.ele.uri.edu/~qyang ------------------------------------------------------------------------ ISCA 2005 Call for Participation 32nd Annual International Symposium on Computer Architecture Madison, Wisconsin (USA) June 4-8, 2005 http://www.cs.wisc.edu/~isca2005/ The 2005 ISCA program has been finalized and online registration is now available (http://www.cs.wisc.edu/~isca2005/register.html). Please be sure to register before May 4th to receive the early registration rates. Discounts have been negotiated for two hotels near the Monona Terrace Convention Center: the Hilton Monona Terrace and the Best Western Inn on the Park. Hotel reservation information can be found on the ISCA 2005 web site: http://www.cs.wisc.edu/~isca2005/hotels.html These discount rates are available until May 4th. The web site also includes an extensive list of attractions to enjoy The web site also includes an extensive list of attractions to enjoy while in Madison (http://www.cs.wisc.edu/~isca2005/thingstodo.html), as well as information about the First (Annual?) ISCA Hockey Game (http://www.cs.wisc.edu/~isca2005/hockey.html) On behalf of all of the organizers of ISCA 2005, we look forward to your participation. ---------------------------------------------------------------------------- Preliminary Call for Papers The 5th IEEE International Symposium on Signal Processing and Information Technology December 18-21, 2005, Athens, Greece The IEEE ISSPIT 2005 is the fifth in a series of international symposia aiming at the coverage of key aspects in the fields of signal processing and information technology. Sessions will include tutorials in addition to presentations on new research results. Papers describing original work are invited in any of the areas of Information Technology and Signal Processing as outlined below. Accepted papers will be published in the Proceedings of IEEE ISSPIT 2005, while acceptance will be based on paper quality, relevance, and originality. A contest for the Best Paper Award will be held and an award will be given. Papers are invited in the following topics: Signal Processing Track: * Signal Processing Theory and Methods * Signal Processing for Communications * DSP architectures and Implementation * DSP for Space Applications/Highly Available Architectures * Multimedia Signal Processing * Image and Multidimensional Signal Processing * Audio and Electro Acoustics * Sensor Array and Multi-channel * Speech Processing * Radar Signal Processing * Neural Networks * Internet Software Architectures Information Technology Track: * Multimedia and Image-based Systems * Mobile Computing and Applications * E-Commerce and Pricing * Bioinformatics and Bioengineering * Information Processing * Geographical Information Systems * Object-based Software Engineering * Speech Processing * Parallel and Distributed Computing * Computer Networks Authors are invited to submit papers of 4 pages as PDF or Postscript files through the online submission system found on the ISSPIT website: http://www.isspit.org. The title page should include author name(s), affiliation, mailing address, telephone, fax, and e-mail address. The author should indicate one or two of the above categories that best describe the topic of the paper. Questions regarding manuscripts should be submitted to the appropriate track Technical Program Co-chair. Important Dates * Proposals for Tutorials and Special Sessions: June 30, 2005 * Four-page paper submission: June 30, 2005 * Notification of acceptance: August 15, 2005 * Final camera-ready copy paper and registration: October 3, 2005 Organizing Committee General Co-chairs: Dimitrios Serpanos, U. of Patras, Greece Ahmed Tewfik, U. of Minnesota, U.S.A. Technical Program Co-chairs Burkhard Stiller, U. of Z?rich and ETH Z?rich, Switzerland (Information Technology Track) Miguel Lagunas, Centre Tecnologic de Telecom. de Catalunya, Spain (Signal Processing Track) Registration and Finance Chair: Reda Ammar, U. of Connecticut, U.S.A. Tutorials Chair: Esam Abdel-Raheem, U. Windsor, Canada Local Arrangement Chair: Christos Douligeris, U. of Pireaus, Greece Web Manager and Publication Chairs: Adel Elmaghraby, U. of Louisville, U.S.A. Mostafa G. Mostafa, WKU, U.S.A. Publicity Chair: Stefanos Kaxiras, U. of Patras, Greece Further information can be obtained from the ISSPIT^?05 Website at http://www.isspit.org. IEEE Approval Pending ########################################################################### CALL FOR PAPERS IISWC 2005 http://www.iiswc.org/ The Annual IEEE International Symposium on Workload Characterization Sponsored by IEEE Computer Society and the Technical Committee on Computer Architecture October 6-8, 2005 The Hotel Marriot at the Capitol Austin, Texas ########################################################################### The meeting that began as Workshop on Workload Characterization (WWC) in 1998 is becoming a Symposium. New computer applications and programming paradigms are constantly emerging to complement new and improving technology. The design of next generation microprocessors and computer systems should be based on an understanding of today's emerging workloads. This 3-day symposium, sponsored by IEEE and the Technical Committee on Computer Architecture, will focus on characterizing and understanding modern computer applications commercial and scientific computing. Papers are solicited in all areas related to characterization of workloads (system and/or application behavior) in a variety of environments. Topics of interest include (but not limited to): - Workload characterization or related studies focusing on the following types of applications: - E-commerce, Web server, Database - Embedded, Mobile, Multimedia - Life Sciences, BioInformatics - Java, Object-oriented - Learning and Discovery, Graphics - Multiprocessor - Scientific and technical - Security, Reliability, Biometrics - Operating system intensive - Multi-threaded - Effects of architectural features on workload behavior - Machine independent characterization of workloads - Memory and I/O access patterns - Power and reliability issues related to workload - Benchmark creation and validation - Representative trace generation - Profiling, trace collection and validation issues - Workload synthesis - Abstract modeling of program behavior - Emerging and Future workloads Important Dates: Abstract Submission: June 20, 2005 Final Paper Submission: June 27, 2005 Acceptance Notified: August 26, 2005 Final Manuscript Submission: September 6, 2005 For more information, visit the ISWC web site at: http://www.iiswc.org/ General Chair Lizy John, The University of Texas at Austin Program Chair David Kaeli, Northeastern University Program Committee Martin Burtscher, Cornell Brad Calder, University of San Diego Dan Connors, University of Colorado Zarka Cvetanovic, HP Marcos de Alba, Tecnol?gico de Monterrey Pradeep Dubey, Intel Lieven Eeckhout, University of Ghent Antonio Gonzalez, UPC Kevin Lepak, AMD Tao Li, University of Florida David Lilja, University of Minnesota Avi Mendelson, Intel Amir Roth, University of Pennsylvania Suleyman Sair, NC State University Julio Sahuquillo, UPV Tim Sherwood, University of Santa Barbara Yan Solihin, NC State University Tilman Wolf, University of Massachusetts Qing Yang, University of Rhode Island Workshop/Tutorial Chair John Kalamatianos, AMD Publicity Chairs Asia: Liza Jo, Philips Research Europe: Salvador Petit, UPV USA: Suleyman Sair, NC State University Publications Chair Ravi Bhargava, AMD Web Chair Byeong Kil Lee, The University of Texas at Austin Registration Chair Joshua Yi, Freescale Semiconductor Finance Chair Kevin Lepak, AMD Industry Liason Jim Bondi, Texas Instruments Steering Committee Pradip Bose, IBM Research Tom Conte, NC State University Lieven Eeckhout, University of Ghent Lizy John, University of Texas at Austin David Kaeli, Northeastern University David Lilja, University of Minnesota Ann Marie Maynard, IBM John Shen, Intel ------------------------------------------------------------------------- HPCA-12 Call for Papers 12th International Symposium on High-Performance Computer Architecture Austin, Texas, February 11-15, 2006 http://www.hpcaconf.org/hpca12 The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture. Topics of interest include, but are not limited to: * Processor architectures * Cache and memory systems * Parallel computer architectures * Impact of technology on architecture * Power-efficient architectures and techniques * High-availability architectures * High-performance I/O systems * Embedded and reconfigurable architectures * Interconnect and network interface architectures * Network processor architectures * Innovative hardware/software trade-offs * Impact of compilers on architecture * Performance evaluation of real machines Authors should submit an abstract before Monday, July 11, 2005, 9pm PST. They should submit the full version of the paper before Monday, July 18, 2005, 9pm PST. No extensions will be granted. The full version should be a PDF file that does not exceed 6,000 words according to the instructions in http://www.hpcaconf.org/hpca12 Papers that exceed the length limit or that cannot be viewed using Adobe Acrobat Reader (version 3.0 or higher) may not be reviewed. Papers should be submitted for blind review. Please indicate whether the paper is a student paper for best student paper nominations. Papers will be evaluated based on their novelty, fundamental insights, and potential for long-term contribution. New-idea papers are encouraged. Submission issues should be directed to the program chair at das@cse.psu.edu. Workshop and tutorial submissions should be directed to the workshop and tutorial chair. Important dates * Abstract submission deadline : July 11, 2005, 9pm PST (firm deadline) * Paper submission deadline: July 18, 2005, 9pm PST (firm deadline) * Workshop and tutorial proposals due: August 12, 2005 * Author notification: October 7, 2005 Sponsored by the IEEE Computer Society TC on Computer Architecture General Co-Chairs: Yale Patt, UT Austin Craig Chase, UT Austin Program Chair: Chita R. Das, Penn State Program Committee: Laxmi Bhuyan, UC Riverside Ricardo Bianchini, Rutgers Univ. David Brooks, Harvard Doug Burger, UT Austin Derek Chiou, UT Austin Frederic T. Chong, UC Davis Dan Connors, Colorado Tom Conte, NCSU Srini Devadas, MIT Jose Duato, Univ. Politecnica Valencia Michel Dubois, USC Rajiv Gupta, Arizona James C. Hoe, CMU Ravi Iyer, Intel Mahmut Kandemir, Penn State Eun Jung Kim, Texas A&M Mikko Lipasti, Univ. of Wisconsin Kai Li, Princeton Scott Mahlke, Michigan Randy Moulic, IBM T.J. Watson Trevor Mudge, Michigan Ashwini Nanda, IBM T.J. Watson Vijaykrishnan Narayanan, Penn State Mark Oskin, Washington Dhabaleswar K. (DK) Panda, OSU Sanjay Patel, UIUC Li-Shiuan Peh, Princeton Milos Prvulovic, GATECH Michael Shebanow, NVIDIA Anand Sivasubramaniam, Penn State Per Stenstrom, Chalmers University of Technology Josep Torrellas, UIUC Dean M. Tullsen, UCSD Mateo Valero, Univ. Politecnica Catalunya Pen-Chung Yew, Minnesota Qing Yang, Rhode Island Raj Yavatkar, Intel Mazin Yousif, Intel Yuanyuan Zhou, UIUC Industry Liaison Chair: Mazin Yousif, Intel Local Arrangements Chair: Derek Chiou, UT Austin Workshop and Tutorial Chair: Yan Solihin Publicity and Publications Chair: Ki Hwan Yum, UT San Antonio Finance and Registration Chair: Craig Chase, UT Austin Web Chair: Vijaykrishnan Narayanan, Penn State Steering Committee: Dharma Agrawal, Univ. of Cincinnati Laxmi Bhuyan, Univ. of California, Riverside Jean-Luc Gaudiot, Univ. of California, Irvine Yale Patt, UT Austin Josep Torrellas, UIUC Justin Rattner, Intel ------------------------------------------------------------------------- HiPEAC 2005 2005 International Conference on High Performance Embedded Architectures & Compilers Barcelona, Spain, 17-18 November 2005 The embedded market evolves rapidly, expanding the capabilities of each new device, and making the previous ones obsolete as technology advances. In order to achieve the high performance required by new embedded applications, these embedded processors are increasingly high-performance processors, with an increasing overlap between general-purpose and embedded processors. However, performance does not simply increase with technology advances, it is essential to find a way to translate technology into performance, and such is the role of the computer architect and compiler builder. The HiPEAC conference provides a high-quality forum for computer architects and compiler builders working in the field of high performance computer architecture and compilation for embedded systems, but is also open to general-purpose research which is becoming increasingly relevant to the embedded domain. The conference aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry. Topics of interest include, but are not limited to: - Processor architectures - Memory system, code size/memory footprint optimizations - Power, performance and implementation efficient designs - Network processors - Security processors - Application specific processors and accelerators - Reconfigurable architectures - Simulation and methodology - Compiler techniques - Feedback-directed optimization - Program characterization and analysis techniques - Dynamic compilation, adaptive execution, and continuous profiling/optimization - Back-end code generation - Binary translation/optimization Conference Web Site: http://www.hipeac.net/hipeac2005 HiPEAC 2005 is collocated right after MICRO-38, The 38th Annual IEEE/ACM International Symposium on Microarchitecture, Barcelona, Spain, November 12-16, 2005 http://www.microarch.org/micro38 PAPER SUBMISSION DEADLINE: June 10, 2005 Submission details and all information concerning the symposium can be found at the conference web site. Acceptance/rejection will be emailed by August 5, 2005. The final manuscript will be due September 10, 2005. General Co-Chairs Tom Conte, NC State University, USA Nacho Navarro, UPC, Spain Program Committee Co-Chairs Mateo Valero, UPC, Spain Wen-mei W. Hwu, UIUC, USA Program Committee David August, Princeton University, USA David Bernstein, IBM Haifa Research Lab, Israel Mike O'Boyle, University of Edinburgh, UK Brad Calder, University of California, USA Jesus Corbal, Intel Labs Barcelona, Spain Alex Dean, NC State University, USA Koen De Bosschere, Ghent University, Belgium Jose Duato, UPV, Spain Marc Duranton, Philips, France Kristian Flautner, ARM Ltd., Cambridge, UK Jose Fortes, University of Florida, USA Roberto Giorgi, Universita di Siena, Italy Rajiv Gupta, University of Arizona, USA Kazuki Joe, Nara Women's University, Japan Manolis Katevenis, ICS, FORTH, Greece Stefanos Kaxiras, University of Patras, Greece Victor Malyshkin, Russian Academy of Sciences, Russia William Mangione-Smith, UCLA, USA Avi Mendelson, Intel, Israel Enric Morancho, UPC, Spain Jaime Moreno, IBM TJ Watson Research, USA Andreas Moshovos, University of Toronto, Canada Trevor Mudge, The University of Michigan, USA Alex Nicolau, University of California, USA Yale Patt, The University of Texas at Austin, USA Antonio Prete, University of Pisa, Italy Alex Ramirez, UPC, Spain Jim Smith, University of Wisconsin, USA Per Strenstrom, Chalmers University, Sweden Olivier Temam, INRIA Futurs, France Theo Ungerer, University of Augsburg, Germany Stamatis Vassiliadis, T.U. Delft, The Netherlands Jingling Xue, University of New South Wales, Australia Publicity Chair Sally A. McKee, Cornell University, USA Publication Chair Theo Ungerer, University of Augsburg, Germany Local Arrangements Co-Chairs Eduard Ayguade, UPC, Spain Josep Llosa, UPC, Spain Registration/Finance Chair Pilar Armas, UPC, Spain Web Chair Michiel Ronsse, Ghent University, Belgium Steering Committee Anant Agarwal, MIT, USA Koen De Bosschere, Ghent University, Belgium Mike O'Boyle, University of Edinburgh, UK Brad Calder, University of California, USA Rajiv Gupta, University of Arizona, USA Wen-mei W. Hwu, UIUC, USA Josep Llosa, UPC, Spain Margaret Martonosi, Princeton University, USA Per Stenstrom, Chalmers University, Sweden Olivier Temam, INRIA Futurs, France ------------------------------------------------------------------------- Call for Papers =============== SBAC-PAD 2005 17th International Symposium on Computer Architecture and High Performance Computing Hotel Pestana, Rio de Janeiro, October 24-27, 2005 http://www.sbc.org.br/sbac/2005 Sponsored by the IEEE Technical Committee on Computer Architecture (TCCA) and the IEEE Technical Committee on Scalable Computing (TCSC) Important Dates =============== Paper submission: May 23, 2005 Author notification: July 4, 2005 Camera-ready copy: July 25, 2005 Tutorial proposals: August 1, 2005 Tutorial notification: August 22, 2005 THE CONFERENCE ============== Held annually since 1987, SBAC-PAD is an international conference that traditionally presents an overview of new developments and trends in computer architecture, parallel and distributed technologies and applications for high performance computing. This year, the symposium will be held in Copacabana, Rio de Janeiro, Brazil. SBAC-PAD welcomes and invites practioners, researchers, developers, faculty members and students around the world to submit manuscripts on all aspects of computer architecture and high performance computing. Topics of interest include (but are not limited to): - Application-specific Architectures; - Cache and Memory Architectures; - Fault-Tolerant Architectures and Systems; - Grid, Cluster, Pervasive and Heterogeneous Computing; - High Performance Applications; - Languages, Compilers and Tools for Parallel and Distributed Programming; - Load Balancing and Scheduling; - Operating Systems; - Processor Microarchitectures; - Parallel and Distributed Algorithms, Architectures, Interconnection Networks, Routing and Communication; - Benchmarking, Performance Measurements and Analysis; - Reconfigurable Systems. FORMAT ====== The goal of the 17th edition of SBAC-PAD is to bring together researchers and practitioners to discuss and exchange ideas with regard to the current state and future direction of research in the specified areas of interest. The symposium aims to combine invited guest lectures, regular presentations, hot topic tutorials and industrial presentations to provide a stimulating and fruitful meeting for all attendees. Proposals for high-quality tutorials in all SBAC-PAD related areas, from academic research to industrial applications, are solicited. Prospective authors of tutorials are invited to submit a preliminary proposal of a two-hour presentation to the Tutorial Chair (Roseli S. Wedemann, roseli@ime.uerj.br), including title, brief description of topics to be covered, and a short biography of the speakers. SUBMISSIONS =========== Manuscripts of original research must be written in English, not exceeding 8 pages in double column using the IEEE style, and be in a PDF or Postscript format. Please check the symposium homepage for more detailed information regarding paper format and electronic submission. All submitted papers will be reviewed internationally for quality, correctness, originality and relevance. At least one of the authors of accepted papers must register and present the paper at the conference. Simultaneous submission to other journals or conferences with published proceedings is not allowed. Once again the best paper award in the area of Applications in High-Performance Systems will be sponsored by NEC do Brasil. Furthermore, authors of selected high quality papers will be invited to submit revised and extended versions for publication in the International Journal of High Performance Computing and Networking (http://www.ijhpcn.org/). ORGANIZATION ============ General Chair: Gabriel P. Silva - NCE/UFRJ Vice-Chair: Vinod Rebello - IC/UFF Program Chairs: Claudio L. Amorim - COPPE/UFRJ Jack Dongarra - University of Tennessee Organizing Committee: Ana L?cia Rodrigues - UFRJ Cristiana Bentes - UERJ Cristina Boeres - UFF Edson T. Midorikawa - USP Maria Clicia S. de Castro - UERJ Mario Jo?o Jr. - UFRJ Roseli S. Wedemann - UERJ S?rgio Guedes - UFRJ STEERING COMMITTEE ================== Alberto F. de Souza (Brazil) Claudio L. Amorim (Brazil) Jairo Panetta (Brazil) Jean-Luc Gaudiot (USA) L?ria M. Sato (Brazil) Philippe O. A. Navaux (Brazil) Rajkumar Buyya (Australia) PROGRAM COMMITTEE ================= Alberto F. de Souza (Brazil) Alfredo Goldman (Brazil) Alvaro L. G. A. Coutinho (Brazil) Bertil Folliot (France) Celso L. Mendes (USA) Cesar A. F. De Rose (Brazil) Christophe C?rin (France) Claudio F. R. Geyer (Brazil) Claudio L. Amorim (Brazil) David Kaeli (USA) Denis Trystram (France) Edil S. T. Fernandes (Brazil) Edson N. C?ceres (Brazil) Eduardo W. Bergamini (Brazil) Evangelos Markatos (Greece) Felipe M. G. Fran?a (Brazil) Frank Dehne (Canada) Gabby Silberman (USA) Guido Ara?jo (Brazil) Hans-Ulrich Heiss (Germany) Horst D. Simon (USA) Howard J. Siegel (USA) Jack Dongarra (USA) Jairo Panetta (Brazil) Jean-Luc Gaudiot (USA) Jos? Fortes (USA) Jos? H. Saito (Brazil) Jos? N. Amaral (Canada) Kazuaki Murakami (Japan) Kuan-Ching Li (Taiwan) Laurence T. Yang (Canada) L?ria M. Sato (Brazil) Liviu Iftode (USA) Luiz DeRose (USA) Manuel Lois Anido (Brazil) Mario Nemirovsky (USA) Mateo Valero (Spain) Nader Bagherzadeh (USA) Orlando G. Loques (Brazil) Osni Marques (USA) Philippe O. A. Navaux (Brazil) Qing (Ken) Yang (USA) Rafael D. Lins (Brazil) Rajkumar Buyya (Australia) Renato S. Silva (Brazil) Ricardo Bianchini (USA) Ron Perrott (UK) Ronaldo A. L. Gon?alves (Brazil) S?rgio Bampi (Brazil) S?rgio T. Kofuji (Brazil) Siang W. Song (Brazil) Tadao Nakamura (Japan) Valmir C. Barbosa (Brazil) Wagner Meira Jr. (Brazil) Walfredo C. Cirne (Brazil) Yale Patt (USA) FOR MORE INFORMATION ==================== For further information, please visit the symposium homepage at http://www.sbc.org.br/sbac/2005 or, for questions regarding the conference program, contact the PC chairs, Claudio L. Amorim (amorim@cos.ufrj.br) or Jack Dongarra (dongarra@cs.utk.edu). For other questions contact the general chair, Gabriel P. Silva (gabriel at nce.ufrj.br). IEEE Technical Committee on Scalable Computing http://www.ieeetcsc.org ------------------------------------------------------------------------- International Workshop on Storage Network Architecture and Parallel I/Os To be held with the 14th International Conference on Parallel Architectures and Compilation Techniques, Saint Louis, Missouri Data are the "life-blood" of computing and the main asset of any organization. Therefore, disk I/O and data storage on which data reside are becoming "first class citizens" in today's information world. This workshop intends to bring together researchers and practitioners from academia and industry to discuss cutting edge research on parallel and distributed data storage technologies. By discussing ongoing research, the workshop will expose participants to the most recent developments in storage network architectures and parallel I/O. Topics of interest include but are not limited to: 1. Storage Manageability, Reliability, Availability, and Security 2. Storage Performance and Scalability 3. File systems, Object-based storage, block-level storage 4. NAS and SAN architectures 5. Storage networking: e.g. Fibre Channel, InfiniBand, IP Storage, iSCSI 6. Parallel I/O architectures 7. Caching and consistency 8. Evaluation of storage architectures 9. Storage management software Organizer: Qing (Ken) Yang Dept. of ECE University of Rhode Island Kingston, RI 02881 Email: qyang@ele.uri.edu Tel: 401-874-5880 Fax: 401-782-6422 Co-Organizer Hong Jiang Dept. of CSE University of Nebraska - Lincoln Lincoln, NE 68588-0115 USA Phone: 402-472-6747 Fax: 402-472-7767 E-mail: jiang@cse.unl.edu ------------------------------------------------------------------------- * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe